Failure mechanism and cause analysis of semiconductor devices

Date：2022-06-28 17:34:48 Views：1823

The quality requirements for the components used in switching power supply and other electronic equipment are also getting higher and higher. With the wide use of semiconductor devices, their life has been degraded and finally led to failure. Failure analysis can deeply understand the failure mechanism and causes, and lead to the improvement of component and product design, which is helpful to improve the reliability of electronic systems.

Researchers have made in-depth research on device failure, established various models or developed various formulas, which can be used to predict when devices fail. These models can not predict when specific devices will fail, but can predict the failure rate of devices under specific conditions with sufficient reasons.

Device failure is usually caused by the stress conditions it is subjected to exceeding its maximum rating. The mode of device failure is called failure mechanism. Generally speaking, electrical stress, thermal stress, chemical stress, radiation stress, mechanical stress and other factors can lead to device failure. It is very important to draw a clear line between failure mechanism and failure cause. For example, devices may fail due to electrical mechanisms caused by mechanical stress.

The common failure mechanisms of semiconductors can be roughly divided into several categories. An in-depth understanding of these mechanisms will help us to accurately determine the device failure and analyze the failure.

1. Failure mechanism and cause analysis

Package failure

When cracks appear in the tube shell, packaging failure will occur. Mechanical stress, thermal stress or mismatch of thermal expansion coefficient between packaging material and metal can lead to crack formation. When the humidity is high or the device contacts with flux, detergent and other substances, these cracks become the path for moisture to invade the tube shell. Chemical reaction can degrade the device, resulting in device failure.

Wire bonding failure

Thermal stress caused by large current, mechanical stress on bonding lead caused by improper bonding, cracks on the interface between bonding lead and chip, electromigration of silicon and excessive bonding pressure will all cause wire bonding failure.

Chip bonding failure

Improper contact between the chip and the substrate can reduce the thermal conductivity between them. Therefore, the chip will overheat, resulting in increased stress and cracking, and eventually make the device invalid.

Bulk silicon defect

Sometimes, the failure caused by crystal defects or the presence of impurities and stains in the silicon material will also make the device invalid. Process defects caused by diffusion problems during device production can also cause device failure.

Oxide layer defect

Electrostatic discharge and high-voltage transients extending through leads can cause breakdown of thin oxide layers, i.e. insulators, and lead to device failure. Cracks and / or scratches in the oxide layer and the presence of impurities in the oxide can also cause device failure.

Aluminum metal defect

These defects are caused by the following reasons:

- electromigration of aluminum in the direction of current due to high electric field;

- damage of aluminum conductor caused by electric over stress caused by large current;

- aluminum corrosion;

- metal wear caused by welding;

- abnormal metal deposition on the contact window;

- formation of hills and cracks.

Devices usually have to undergo a specific event or a group of conditions before they fail. The rest of this article describes the most common events or conditions that can cause a failure. By understanding these reasons, technicians can conduct in-depth failure analysis to produce more reliable products. However, it must be kept in mind that design defects in devices, PCBs, or end products can create conditions that can lead to device failure.

2. Thermal Overstress

Thermal overstress can cause semiconductor failure. High temperature will melt metal materials, carbonize and warp plastics, damage semiconductor chips, and cause other types of damage. Generally speaking, the device should not work at junction temperature above 125 ~ 150 ℃. For military products, the junction temperature should be limited to 110 ℃. Using Arrhenius formula, we can see that the failure rate can be reduced by half when the junction temperature of the device is reduced from 160 ℃ to 135 ℃.

If the failure is caused by high temperature, the product designer shall be informed. Designers must reconsider the product packaging and working specifications to ensure that fans, fins and other cooling devices can keep the components within the temperature range specified in the specifications. High power devices need heat sinks and fans to cool, while low-power devices can simply diffuse heat into the surrounding air. In this way, the test engineer must ensure that the heat sink and fan are in proper position during the test period, or that other heat dissipation devices can be sufficient to cool the devices under test.

The test engineer must also monitor the temperature changes of power semiconductors and components to ensure that they work normally at a safe temperature.

3. Electrical overstress

Semiconductor devices shall operate within the voltage and current range and power limit specified by the manufacturer. When the device operates under these safe working conditions, the electrical overstress will cause the internal voltage breakdown of the device, which will damage the device. If the electric over stress produces a large current, the device will overheat. This kind of thermal over stress becomes the failure factor of the accelerator.

Circuit designers can minimize electrical overstress failure by reducing the amount of components used. In addition, in the circuit design, adding protectors such as zener diodes, rheostats and filters is an effective measure to prevent over stress from reaching key devices.

Whether in the manufacturing, testing, handling, assembly, production or use stages of devices, electrostatic discharge (ESD) will damage the functions of electronic devices. As electricity is generated by friction, people walking on the carpet can generate static electricity as high as 20kV. In addition, machines using plastic parts will also generate electrostatic discharge. Obviously, if this kind of static electricity is diffused into semiconductors, it will inevitably damage the devices.

ESD does not necessarily invalidate the device immediately. It can cause potential defects in the device, which are difficult to detect in the test phase. When the system operates under actual working conditions, such weakened devices may fail soon.

Generally speaking, ESD damage is shown in the following ways:

- damage to devices caused by discharge or electric over stress. The damage will lead to the generation of current greater than the normal current, resulting in the generation of thermal overstress. Thermal overstress will melt the metal interconnects and cause damage to the junctions.

- strong electric field causes breakdown of junction and thin oxide layer.

- the electric field caused by ESD can be coupled with PCB lines and generate a large current that can melt the semiconductor junction.

- due to the triggering of SCR, the discharge will cause "latch up" in CMOS devices.

The failure analysis shows that the latch caused by ESD is one of the causes of device failure. CMOS integrated circuits are particularly vulnerable to ESD and latch UPS because of their parasitic pnpn structure.

In order to minimize the failure caused by ESD, the following measures must be taken:

- electronic components shall be stored in tubes or boxes that can diffuse static electricity;

- when manual welding, workers shall use grounding terminal welding equipment;

- anti static workbench and floor shall be used;

- the components shall be packed in bags that can diffuse static electricity.

Mil-std-883 and 1686 provide component standards, iec1000-4-2 and eia1361 provide equipment standards, and American ESD Association formulates device handling standards.

Device failure mainly comes from two kinds of problems: one is the problem of missing the initial test of the device batch, and the other is the problem in the device design. Sometimes, the failure of super constant occurs in the device batch. These devices have passed the initial production test, but improper handling, improper packaging methods and problems in assembly, testing and shipping have caused potential defects in the devices. According to these conditions, it is necessary to re evaluate the input test, handling and other processes, and work closely with suppliers to tighten product specifications.