Description:

ESD (Electrostatic discharge) is the release of static electricity when two objects come into contact. Static electricity is a natural phenomenon with various generation methods such as contact or friction, etc. Static electricity is characterized by high voltage, low power, small current, and short duration.

EOS (Electrical Over-Stress) refers to all forms of excessive electrical stress. It is the thermal damage that may occur when an electronic device is subjected to a current or voltage that is beyond the specification limits of the device.

Latch-up refers to a condition where a low-impedance path in CMOS due to the interaction of parasitic PNP and NPN bipolar junction transistors between the power supply (VDD) and ground (GND or VSS) lines.

Latch-up is defined as the creation of a low impedance path between the power VDD and the ground VSS by the triggering of parasitic PNP and NPN bipolar structures (SCR’s) inherent in CMOS input and output circuitry.

Testing helps identify the vulnerabilities and electrostatic tolerance of ICs, providing a basis for subsequent system design adjustments, chip circuit design adjustments, and even RMA failure analysis.

Scope of Application: 

Chip components and finished modules.

Test Modes:

Human Body Mode Test;

Machine Mode Test;

Charged Device Mode Test;

Latch-up Test;

Transient-Induced Latch up Test;

System ESD Test–ESD Gun Test;

ESD I-V Curve Measurement;

Electrical Over Stress Test.

Gate Voltage Scanning Curve:

Voltage shift over ±30% at reference point.

Images of Testing Equipment: