Description:

In order to remove the multi-layer structure of the chip itself (passivation, metal, ILD), various processing methods are used in repetitive combination, such as ion etching, chemical etching, or mechanical grinding. This allows for the step-by-step removal of each layer, known as delayering. Through chip polishing and delayering, each layer can be inspected for defects to enable clearly presenting circuit layout structure of each layer for later experiments.

Scope of Application:

All packaged ICs.

Images of IC Delayer Testing:

IC delayer → OM reviewing → Contact layer → SUB layer

IC delayer to SUB → OM viewing and imaging →SEM electronic and secondary electronic scanning